Team DaRT

Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Other Grants and Activities
Dissemination
Bibliography

Section: New Results

Experimental validation

Participants : Rabie Ben Atitallah, Pierre Boulet, Jean-Luc Dekeyser, Frédéric Guyomarc'h, Sébastien Le Beux, Philippe Marquet, Samy Meftali, Smaïl Niar, Julien Taillard.

Anti-collision detection radar

In the scope of the European ModEasy project, we had the opportunity to participate to the implementation of a radar anti-collision system for vehicles. In collaboration with the INRETS (http://www.inrets.fr/infos/centres/ct_vascq.html )from Lille (Institut National de Recherche sur les Transports et leur Sécurité) and the IEMN (http://www.iemn.univ-lille1.fr/ )from Valenciennes (Institut d'Electronique de Microélectronique et de Nanotechnologie), we validated the behavior of the correlation algorithm used for obstacle detection during on road real condition tests  [Oops!] .

MPSoC simulation in SystemC

MultiProcessor Systems-on-Chip (MPSoC) architecture has become a solution for designing embedded systems dedicated to applications that require intensive computations. The most important design challenges in such systems consist in reducing simulation time and estimating performance appropriately. In our work, we focus on the use of Transaction Level Modeling (TLM) in an MPSoC design which corresponds to a set of abstraction levels that simplifies the description of inter-module communication transactions using objects and channels between the communicating modules. Consequently, modeling MPSoC architectures becomes easier and faster than at the CABA (Cycle Accurate Bit Accurate) level.

As our objective is to propose reliable environment for rapid MPSoC design space exploration, the framework has been designed in the context of PVT (Timed Programmer View) level. In the conventional definition of the PVT level, the hardware architecture is specified for both processing and communication parts, as well as some arbitration of the communication infrastructure is applied. In addition for performance estimation, this level is annotated with timing specification.

In this context, we have proposed a new PVT approach, containing three sublevels namely PVT-PA (Pattern Accurate), PVT-TA (Transaction Accurate) and PVT-EA (Event Accurate). These sub-levels are intended to increase the speed of MPSoC simulation. Several component models have been developed using these three sublevels and enhanced with performance and power consumptions estimation tools to provide accurate execution time and power consumption estimates. Simulation results demonstrate the complementarity between the proposed sublevels which provide different simulation speedup/accuracy trade-offs  [Oops!] .

High-performance computing

The solver part of CARMEL has been modelled with Gaspard2. This work was done in two parts: first, the design of the high-level model, and then the choice of the IP for the building blocks of the solver. Different algorithms and different libraries of IP have been tested to exhibit the most efficient ones. These results have also been validated with the ones produced by the original FORTRAN code of CARMEL.

Massively parallel processing SoC

We are working on the definition and design of mppSoC, a massively parallel system on a chip. The objective of the mppSoC project is to reconsider the interest of massively parallel machines with nowadays design methodologies based on IP reuse and nowadays integration technologies.

MppSoC is a SIMD architecture composed of a grid of processing elements (the PEs) and memories connected by a regular neighbourhood network and a general purpose global network.

Some improvements of the system architecture are possible because of the high degree of integration: The mppSoC PEs share most of their design with the control processor, the integrated network allows to exchange data between PEs, but also between the control processor and the PE memories, and even to connect the external devices to the system.

The first works in the project have already led to the design of a cycle-accurate bit-accurate SystemC simulator of the architecture, and to an implementation prototype on FPGA. A complete tool chain based on an data-parallel language allows to generate binary programs that execute both on the simulator and the hardware implementation. We have been able to integrate 16 processing elements in a single FPGA  [Oops!] .

We are now considering the redesign of the mppSoC as a set of IPs. Then, from theses IPs, a generic design of a parametrized mppSoC system will be possible. The parametrization of a mppSoC system will defined the number of PEs, the amount of memory, the kind of network required for a specific system that will be design for a given application or class of applications. The whole mppSoC design chain is impacted by this new characteristics.


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