Team DaRT

Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Other Grants and Activities
Dissemination
Bibliography

Bibliography

Major publications by the team in recent years

[1]
A. C. Aljundi, J.-L. Dekeyser, M. T. Kechadi, I. D. Scherson.
A universal performance factor for multi-criteria evaluation of multistage interconnection networks., in: Future Generation Comp. Syst., 2006, vol. 22, no 7, p. 794-804.
[2]
R. Ben Atitallah, É. Piel, S. Niar, P. Marquet, J.-L. Dekeyser.
Multilevel MPSoC simulation using an MDE approach, in: IEEE International SoC Conference (SoCC 2007), Hsinchu, Taiwan, September 2007.
[3]
P. Boulet, C. Dumoulin, A. Honoré.
Model Driven Engineering for System-on-Chip Design, in: From MDD concepts to experiments and illustrations, S. Gérard, J.-P. Babeau, J. Champeau (editors), ISBN:1-905209-59-0, ISTE, September 2006
http://iste.co.uk/index.php?f=a&ACTION=View&id=147.
[4]
P. Boulet, P. Marquet, É. Piel, J. Taillard.
Repetitive Allocation Modeling with MARTE, in: Forum on specification and design languages (FDL'07), Barcelona, Spain, Invited paper, September 2007.
[5]
A. Cuccuru, J.-L. Dekeyser, P. Marquet, P. Boulet.
Towards UML 2 extensions for compact modeling of regular complex topologies, in: MODELS/UML 2005, ACM/IEEE 8th international conference on model driven engineering languages and systems, Montego Bay, Jamaica, October 2005.
[6]
A. Gamatié, T. Gautier, P. Le Guernic, J.-P. Talpin.
Polychronous Design of Embedded Real-Time Applications, in: ACM Transactions on Software Engineering and Methodology (TOSEM), April 2007, vol. 16, no 2.
[7]
O. Labbani, J.-L. Dekeyser, É. Rutten.
Safe Design Methodology for an Intelligent Cruise Control System with GPS, in: VTC'2006 Fall: 64th IEEE Vehicular Technology Conference, Montréal, Québec, Canada, (Also to appear as an IEEE ITSS Newsletter in December 2006), September 2006.
[8]
S. Le Beux, P. Marquet, J.-L. Dekeyser.
A Design Flow to Map Parallel Applications onto FPGAs, in: 17th IEEE International Conference on Field Programmable Logic and Applications, FPL, Amsterdam, Netherlands, August 2007.
[9]
P. Marquet, S. Duquennoy, S. Le Beux, S. Meftali, J.-L. Dekeyser.
Massively Parallel Processing on a Chip, in: ACM Int'l Conf. on Computing Frontiers, Ischia, Italy, May 2007.
[10]
S. Meftali, J. Vennin, J.-L. Dekeyser.
Automatic Generation of Geographically Distributed System Simulation Models for IP/SoC Design, in: The 46th IEEE International Symposium on Circuits and Systems, Cairo, Egypt, December 2003.
[11]
H. Sbeyti, S. Niar, L. Eeckhout.
Pattern-Driven Prefetching for Multimedia Applications on Embedded Processors, in: Journal of System Architecture, April 2006, vol. 52, no 4, p. 199-212.

Publications of the year

Doctoral dissertations and Habilitation theses

[12]
S. Le Beux.
Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGA à base d'Ingénierie Dirigée par les Modèles, Thèse de doctorat (PhD Thesis), Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, France, December 2007.
[13]
É. Piel.
Ordonnancement de systèmes parallèles temps-réel, De la modélisation à la mise en œuvre par l'ingénierie dirigée par les modèles, Thèse de doctorat (PhD Thesis), Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, France, December 2007.

Articles in refereed journals and book chapters

[14]
C. Dumoulin, A. Etien.
Morphing de métamodèles, in: L'Objet, October-December 2007, vol. 13, no 4, p. 33-35
http://objet.e-revues.com/article.jsp?articleId=11241.
[15]
A. Gamatié, T. Gautier, P. Le Guernic, J.-P. Talpin.
Polychronous Design of Embedded Real-Time Applications, in: ACM Transactions on Software Engineering and Methodology (TOSEM), April 2007, vol. 16, no 2.
[16]
O. Labbani, Jean-Luc. Dekeyser, P. Boulet, É. Rutten.
18, in: UML2 profile for modelling controlled data parallel applications, ISBN: 978-1-4020-6147-9, Sorin A. Huss editor, Springer Verlag, September 2007.

Publications in Conferences and Workshops

[17]
R. Atitallah, S. Niar, J.-L. Dekeyser.
MPSoC Power Estimation Framework at Transaction Level Modeling, in: 19th International Conference on Microelectronics (ICM 2007), Cairo, Egypt, December 2007.
[18]
Y. Aydi, S. Meftali, M. Abid, J.-L. Dekeyser.
Dynamicity Analysis of Delta MINs for MPSoC Architectures, in: Conférence internationale des Sciences et Techniques de l'Automatique (STA'07), November 2007.
[19]
R. Ben Atitallah, S. Niar, S. Meftali, J.-L. Dekeyser.
An MPSoC performance estimation framework using transaction level modeling, in: IEEE RTCSA'2007, Daegu, Korea, August 2007.
[20]
R. Ben Atitallah, É. Piel, S. Niar, P. Marquet, J.-L. Dekeyser.
Multilevel MPSoC simulation using an MDE approach, in: IEEE International SoC Conference (SoCC 2007), Hsinchu, Taiwan, September 2007.
[21]
R. Ben Atitallah, É. Piel, J. Taillard, S. Niar, J.-L. Dekeyser.
From High Level MPSoC description to SystemC Code Generation, in: International ModEasy'07 Workshop in conjunction with Forum on specification and Design Languages (FDL'07), Barcelona, Spain, September 2007.
[22]
A. E. H. Benyamina, P. Boulet.
Multi-objective Mapping for NoC Architectures, in: 1st International Conference on Digital Communications and Computer Applications, Jordan, March 2007, p. 132-139.
[23]
P. Boulet, P. Marquet, É. Piel, J. Taillard.
Repetitive Allocation Modeling with MARTE, in: Forum on specification and design languages (FDL'07), Barcelona, Spain, Invited paper, September 2007.
[24]
J.-L. Dekeyser, S. Le Beux, P. Marquet.
Une approche modèle pour la conception conjointe de systèmes embarqués hautes performances dédiés au transport, in: Workshop International : Logistique & Transport (LT'2007), November 2007.
[25]
S. Kamoun, P. Boulet.
Model-Based Testing of the ERTMS System with SysML and MARTE, in: MoDeVVa'07 (integrating V&V in MDE), Nashville, USA, October 2007.
[26]
S. Kamoun, P. Boulet.
Une approche modèle pour la génération de scénarios de tests : Application au système ERTMS/ETCS, in: Workshop International : Logistique and Transport 2007, Sousse, Tunisie, November 2007.
[27]
S. Le Beux, P. Marquet, J.-L. Dekeyser.
A Design Flow to Map Parallel Applications onto FPGAs, in: 17th IEEE International Conference on Field Programmable Logic and Applications, FPL, Amsterdam, Netherlands, August 2007.
[28]
S. Le Beux, P. Marquet, J.-L. Dekeyser.
Multiple Abstraction Views of FPGA to Map Parallel Application, in: 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips, ReCoSoC, Montpellier, France, June 2007.
[29]
S. Le Beux, P. Marquet, A. Honoré, J.-L. Dekeyser.
A Model Driven Engineering Design Flow to Generate VHDL, in: International ModEasy'07 Workshop, Barcelona, Spain, September 2007
http://www2.lifl.fr/modeasy/workshop.html.
[30]
P. Marquet, S. Duquennoy, S. Le Beux, S. Meftali, J.-L. Dekeyser.
Massively Parallel Processing on a Chip, in: ACM Int'l Conf. on Computing Frontiers, Ischia, Italy, May 2007.
[31]
Imran Rafiq. Quadri, S. Meftali, J.-L. Dekeyser.
An MDE Approach for Implementing Partial Dynamic Reconfiguration in FPGAs, in: 16th International Workshop on IP Based System-on-chip, IP'07, Grenoble, France, December 2007.
[32]
S. Taha, A. Radermacher, J.-L. Dekeyser, S. Gerard.
MARTE: UML-based Hardware Design from Modeling to Simulation, in: Forum on specification and Design Languages - FDL'07, Barcelona - Spain, September 2007.
[33]
S. Taha, A. Radermacher, S. Gérard, J.-L. Dekeyser.
An Open Framework for Detailed Hardware Modeling, in: International Symposium on Industrial Embedded Systems (SIES '07), July 2007.
[34]
H. Yu, A. Gamatié, É. Rutten, Jean-Luc. Dekeyser.
Model Transformations from a Data Parallel Formalism towards Synchronous Languages, in: Forum on specification and Design Languages - FDL'07, Barcelona - Spain, September 2007.

Internal Reports

[35]
R. Ben Atitallah, P. Boulet, A. Cuccuru, J.-L. Dekeyser, A. Honoré, O. Labbani, S. Le Beux, P. Marquet, É. Piel, J. Taillard, H. Yu.
Gaspard2 UML profile documentation, Technical Report, INRIA, September 2007, no 0342
http://hal.inria.fr/inria-00171137/en.
[36]
P. Boulet.
Array-OL Revisited, Multidimensional Intensive Signal Processing Specification, Research Report, INRIA, feb 2007, no RR-6113
http://hal.inria.fr/inria-00128840/en.
[37]
A. Etien, C. Dumoulin, E. Renaux.
Towards a Unified Notation to Represent Model Transformation, Research Report, INRIA, May 2007, no RR-6187
https://hal.inria.fr/inria-00145204.
[38]
H. Yu, A. Gamatié, É. Rutten, Jean-Luc. Dekeyser.
Model Transformations from a Data Parallel Formalism towards Synchronous Languages, Rapport de Recherche, INRIA, September 2007, no 6291
http://hal.inria.fr/inria-00172302.

References in notes

[39]
Object Management Group, Inc. (editor)
U2 Partners' (UML 2.0): Superstructure, 2nd revised submission, January 2003
http://www.omg.org/cgi-bin/doc?ptc/03-01-02.
[40]
Object Management Group, Inc. (editor)
(UML 2.0): Superstructure Draft Adopted Specification, July 2003
http://www.omg.org/cgi-bin/doc?ptc/03-07-06.
[41]
M. D. Adams.
The JPEG-2000 Still Image Compression Standard, Technical report, ISO/IEC JTC 1/SC 29/WG 1, September 2001, no N2412.
[42]
A. Amar, P. Boulet, P. Dumont.
Projection of the Array-OL Specification Language onto the Kahn Process Network Computation Model, in: International Symposium on Parallel Architectures, Algorithms, and Networks, Las Vegas, Nevada, USA, December 2005
http://sigact.acm.org/ispan05/.
[43]
C. Bastoul.
Code Generation in the Polyhedral Model Is Easier Than You Think, in: PACT'13 IEEE International Conference on Parallel Architecture and Compilation Techniques, Juan-les-Pins, September 2004, p. 7–16.
[44]
A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, R. de Simone.
The Synchronous Languages Twelve Years Later, in: Proceedings of the IEEE, January 2003, vol. 91, no 1, p. 64-83.
[45]
G. Berry.
The Foundations of Esterel, in: Proof, Language and Interaction: Essays in Honour of Robin Milner, MIT Press, 1998
http://www-sop.inria.fr/meije/esterel/doc/main-papers.html.
[46]
L. Bondé.
Transformations de Modèles et Interopérabilité dans la Conception de Systèmes Hétérogènes sur Puce à base d'IP, Doctorat en Informatique, Université des Sciences et Technologies de Lille, December 2006.
[47]
P. Boulet.
Array-OL Revisited, Multidimensional Intensive Signal Processing Specification, Research Report, INRIA, February 2007, no RR-6113
http://hal.inria.fr/inria-00128840/en.
[48]
P. Boulet, J.-L. Dekeyser, J.-L. Levaire, P. Marquet, J. Soula, A. Demeure.
Visual Data-parallel Programming for Signal Processing Applications, in: 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, Mantova, Italy, February 2001, p. 105–112.
[49]
P. Caspi, D. Pilaud, N. Halbwachs, J.A. Plaice.
Lustre: a declarative language for real-time programming, in: Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages (POPL'87), ACM Press, 1987, p. 178-188.
[50]
A. Demeure, A. Lafage, E. Boutillon, D. Rozzonelli, J.-C. Dufourd, J.-L. Marro.
Array-OL : Proposition d'un Formalisme Tableau pour le Traitement de Signal Multi-Dimensionnel, in: Gretsi, Juan-Les-Pins, France, September 1995.
[51]
A. Demeure, Y. Del Gallo.
An Array Approach for Signal Processing Design, in: Sophia-Antipolis conference on Micro-Electronics (SAME 98), France, October 1998.
[52]
P. Dumont, P. Boulet.
Transformations de code Array-OL : implémentation de la fusion de deux tâches, Technical report, Laboratoire d'Informatique fondamentale de Lille et Thales Communications, October 2003.
[53]
P. Dumont.
Étude des Transformations d'un Code Array-OL dans Gaspard, Research Report, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille , France, September 2002, no 02-11
http://www.lifl.fr/LIFL1/publications/2002-11.ps.
[54]
P. Dumont.
Spécification multidimensionnelle pour le traitement du signal systématique, (In French), Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, 2005.
[55]
Eclipse Consortium.
The Eclipse Project, 2003
http://www.eclipse.org.
[56]
Eclipse Consortium.
EMF Eclipse Modeling Framework, 2007
http://www.eclipse.org/emf.
[57]
Esterel Technologies.
SoC Design, Validation and Verification, 2002
http://www.esterel-technologies.com/v3/?id=29453.
[58]
D. D. Gajski, R. Kuhn.
Guest Editor Introduction: New VLSI-Tools, in: IEEE Computer, December 1983, vol. 16, no 12, p. 11-14.
[59]
C. Glitia.
Code transformations for systematic signal processing and memory size optimizations, Master recherche, Université des sciences et technologies de Lille, 2006.
[60]
N. Kadri, S. Niar, A. Baba-Ali.
Impact of Code Compression on the Power Consumption in Embedded Systems, in: international conference on Embedded Systems and Applications ESA'03, June 2003.
[61]
G. Kahn.
The Semantics of a Simple Language for Parallel Programming, in: Information Processing 74: Proceedings of the IFIP Congress 74, J. L. Rosenfeld (editor), North-Holland, IFIP, August 1974, p. 471–475.
[62]
G. Kahn, D. B. MacQueen.
Coroutines and networks of parallel processes, in: Information Processing 77: Proceedings of the IFIP Congress 77, B. Gilchrist (editor), North-Holland, 1977, p. 993–998.
[63]
A. Koudri, D. Aulagnier, J. Champeau.
FPGA design based on UML/MDA Approach: Application to an RF Tranceiver development, in: 4th workshop on tUML for SoC Design, June 2007.
[64]
A. Koudri, D. Aulagnier, J. Champeau.
Une sémantique opérationnelle pour une meilleure métamodélisation, in: Atelier sur la Sémantique des Modèles, march 2007.
[65]
O. Labbani, É. Rutten, J.-L. Dekeyser.
Safe Design Methodology for an Intelligent Cruise Control System with GPS, December 2006, IEEE Intelligent Transportation Systems Society Newsletter, vol. 8, nr. 4, pp. 16-23.
[66]
P. Le Guernic, J.-P. Talpin, J.-C. Le Lann.
Polychrony for System Design, in: Journal for Circuits, Systems and Computers, April 2003, vol. 12, no 3, p. 261–304.
[67]
A. Meena, P. Boulet.
Model Driven Scheduling Framework for Multiprocessor SoC Design, in: Workshop on Scheduling for Parallel Computing, SPC 2005, Poznan, Poland, September 2005
http://www.cs.put.poznan.pl/mdrozdowski/spc-ppam05/.
[68]
S. Meftali, J.-L. Dekeyser, Isaac D. Scherson.
Scalable Multistage Networks for Multiprocessor System-on-Chip Design, in: International Symposium on Parallel Architectures, Algorithms, and Networks, Las Vegas, Nevada, USA, December 2005
http://sigact.acm.org/ispan05/.
[69]
P. K. Murthy, E. A. Lee.
Multidimensional Synchronous Dataflow, in: IEEE Transactions on Signal Processing, July 2002.
[70]
P. K. Murthy.
Scheduling Techniques for Synchronous and Multidimensional Synchronous Dataflow, Ph. D. Thesis, University of California, Berkeley, CA, 1996.
[71]
S. Niar, L. Eeckhout, K. DeBosschere.
Comparing multiported cache schemes, in: PDPTA-2003, June 2003.
[72]
Object Management Group, Inc..
MOF 2.0 Query / Views / Transformations RFP, OMG paper, 2003.
[73]
Object Management Group, Inc..
Meta Object Facility (MOF) Core Specification, Version 2.0, January 2006
http://www.omg.org/docs/formal/06-01-01.pdf.
[74]
OpenMP Architecture Review Board.
OpenMP Application Programme Interface, May 2005
http://www.openmp.org/drupal/mp-documents/spec25.pdf.
[75]
Open SystemC Initiative.
SystemC, 2002
http://www.systemc.org/.
[76]
H. Sbeyti, S. Niar, L. Eeckhout.
Adaptive Prefetching for Multimedia Applications in Embedded Systems, in: DATE'04, Paris, France, EDA IEEE , February 2004.
[77]
D. Schmidt.
Model-Driven Engineering, in: IEEE Computer, February 2006, vol. 39, no 2, p. 41-47.
[78]
Y. Sorel.
Massively Parallel Computing Systems with Real Time Constraints - The “Algorithm Architecture Adequation” Methodology, in: Proceedings of the 1st International Conference on Massively Parallel Computing Systems, Los Alamitos, CA, USA, IEEE Computer Society Press, May 1994, p. 44–54.
[79]
J. Soula.
Principe de Compilation d'un Langage de Traitement de Signal, (In French), Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, December 2001.
[80]
J. Taillard, F. Guyomarc'h, J.-L. Dekeyser.
A Graphical Framework for High Performance Computing using an MDE Approach, in: 16th Euromicro International Conference on Parallel, Distributed and network-based Processing, Toulouse, France, to appear, February 2008.
[81]
Virtutech.
Simics Platform, 2007
http://www.virtutech.com.

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