Team R2D2

Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Other Grants and Activities
Dissemination
Bibliography

Bibliography

Major publications by the team in recent years

[1]
F. Charot, G. Le Fol, P. Lemonnier, C. Wagner, C. Bouville, R. Barzic.
Towards Hardware Building Blocks for Software-Only Real Time Video Processing: the MOVIE Approach, in: IEEE Transactions on Circuits and Systems for Video Technology, September 1999, vol. 9, no 6.
[2]
R. David, D. Chillet, S. Pillement, O. Sentieys.
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals, in: SOC Design Methodologies, Kluwer Academic Publishers, 2002, p. 51–62.
[3]
R. David.
Architecture reconfigurable dynamiquement pour applications mobiles, Thèse de Doctorat, Université de Rennes, July 2003.
[4]
F. Dupont de Dinechin.
Systèmes structurés d'équations récurrentes : mise en œuvre dans le langage Alpha et applications, Thèse de doctorat, université de Rennes I, January 1997.
[5]
K. Kuchcinski, C. Wolinski.
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, December 2003, vol. 49, no 12-15.
[6]
C. Mauras.
Alpha : un langage équationnel pour la conception et la programmation d'architectures parallèles synchrones, Thèse de doctorat, Université de Rennes 1, December 1989.
[7]
D. Ménard.
Méthodologie de compilation d'algorithmes de traitement du signal en précision infinie pour les processeurs en virgule fixe, Thèse de doctorat, Université de Rennes 1, December 2002.
[8]
V. Messé.
Production de compilateurs flexibles pour la conception de processeurs programmables spécialisés, Thèse de doctorat, Université de Rennes 1, March 1999.
[9]
P. Quinton, V. V. Dongen..
The mapping of linear recurrence equations on regular arrays, in: Journal of VLSI Signal Processing, 1989, vol. 1, p. 93-113.
[10]
P. Quinton, Y. Robert.
Systolic Algorithms and Architectures, Prentice Hall and Masson, 1989.
[11]
C. Wolinski, M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, no 4-6.

Publications of the year

Doctoral dissertations and Habilitation theses

[12]
S. Chevobbe.
Unité de commande pour systèmes parallèles : contrôleur basé sur l'implémentation dynamique de réseaux de Pétri, Thèse de Doctorat, Université de Rennes 1, October 2005.
[13]
M. Nyamsi.
Prototypage d'architectures pour des applications de traitement numérique du signal, Thèse de Doctorat, Université de Rennes 1, November 2005.
[14]
J.-M. Philippe.
Intégration des réseaux sur silicium : optimisation des couches physique et liaison, Thèse de Doctorat, Université de Rennes 1, November 2005.

Articles in refereed journals and book chapters

[15]
M. Auguin, O. Sentieys.
Conception de systèmes sur puce : nécessité d'approches globales face à la concentration des difficultés, in: Etat des lieux en Architecture, Parallélisme et Système, M. Jemni, D. Trystram (editors), to appear, Hermes, 2005.
[16]
M. Bellanger, J. Brossier, J. Delmas, A. Gilloire, F. Michaut, P. Regalia, P. Scalart.
Filtrage RIF adaptatif, in: Filtrage adaptatif : Théorie et algorithmes, sous la direction de F. MICHAUT et M. BELLANGER, to appear, 2005.
[17]
P. Benoit, G. Sassatelli, L. Torres, G. Cambon, D. Demigny.
Méthode de Caractérisation des Architectures d'Accélérateurs Flexibles pour Systèmes sur Puce, in: Technique et Science Informatiques, 2005, vol. 24, no 6.
[18]
D. Chillet, L. Abdelouel, D. Menard, N. Hervé, S. Pillement, O. Sentieys.
Modèle générique de hiérarchie mémoire pour l'exploration architecturale, in: Technique et Science Informatiques, numéro spécial Architecture, to appear, 2005.
[19]
D. Chillet, R. David, E. Grace, O. Sentieys.
Hiérarchie mémoire reconfigurable :Premiers pas vers la faible consommation, in: Technique et Science Informatiques, numéro spécial Faible Consommation, to appear, 2005.
[20]
R. David, D. Lavenier, S. Pillement.
Du microprocesseur au circuit FPGA : une analyse sous l'angle de la reconfiguration, in: Technique et Science Informatiques, 2005, vol. 24, no 4, p. 395–422.
[21]
A. Derrien, C. Zissulescu, B. Kienhuis, E. Deprettere.
Deriving Efficient Control in Process Networks with Compaan/laura, in: International Journal of Embedded Systems, 2005.
[22]
S. Guyetant, M. Giraud, L. L'Hours, S. Derrien, S. Rubini, D. Lavenier, F. Raimbault.
Cluster of Reconfigurable Nodes for Scanning Large Genomic Banks, in: Parallel Computing, 2005, vol. 31, no 1, p. 73–96.
[23]
L. Kessal, N. Abel, D. Demigny.
Traitement temps réel des images en exploitant la reconfiguration dynamique : architecture et programmation, in: Traitement du Signal, to appear, 2005.
[24]
D. Menard, D. Chillet, O. Sentieys.
Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing, Special issue on Design Methods for DSP Systems, to appear, 2005.
[25]
C. Plapous, C. Marro, P. Scalart.
Improved signal-to-noise ratio estimation for speech enhancement, in: IEEE Transactions on Speech and Audio Processing, to appear, 2005.

Publications in Conferences and Workshops

[26]
L. Abdelouel, D. Chillet, O. Sentieys.
Synthèse de l'interconnexion des mémoires dans un contexte multi-processeurs, in: Majestic 2005, Troisième MAnifestation des JEunes Chercheurs dans les domaines STIC, Rennes, France, 2005.
[27]
I. Benkermi, A. Benkhelifa, D. Chillet, S. Pillement, J. Prevotet, F. Verdier.
Modélisation niveau système de SoC reconfigurables, in: RENPAR’16 / CFSE’4 / SympAAA’2005 / Journées Composants, Le Croisic, France, 2005.
[28]
I. Benkermi, A. Benkhelifa, D. Chillet, S. Pillement, J. Prévotet, F. Verdier.
System-Level Modelling for Reconfigurable SoCs, in: DCIS'05, XX Conference on Design of Circuits and Integrated Systems, Lisboa - Portugal, 2005.
[29]
O. Berder, P. Rostaing, G. Burel.
Inter-channel interference rejection for maritime AIS system, in: Proceedings of the 5th International Conference on ITS Telecommunications, Brest, France, 2005, p. 105–108.
[30]
S. Bruno, P. Scalart.
Estimation of cardiac and Respiratory rhythms based on an AMFM demodulation and an adaptive eigenvector decomposition, in: EUSIPCO 2005, 13th European Signal Processing Conference, Antalya, Turkey, 2005.
[31]
F. Charot, M. Nyamsi, P. Quinton, C. Wagner.
Prototypage rapide à l'aide de la plate-forme SignalMaster de LSP: étude de cas du WCDMA, in: Proceedings of the Journées Francophones sur l'Adéquation Algorithme Architecture, Dijon, France, January 2005.
[32]
D. Chillet, L. Abdelouel, O. Sentieys.
Modèle générique de hiérarchie mémoire pour l’exploration architecturale, in: RENPAR’16 / CFSE’4 / SympAAA’2005 / Journées Composants, Le Croisic, France, 2005.
[33]
H. Daasi, P. Scalart, C. Marro.
A centralized acoustic echo canceller based on perceptual properties, in: EUSIPCO 2005, 13th European Signal Processing Conference, Antalya, Turkey, 2005.
[34]
A. Darte, S. Derrien, T. Risset.
Hardware/Software Interface for Multi-Dimensional Processor Arrays, in: IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2005.
[35]
F. Hannig, H. Dutta, A. Kupriyanov, J. Teich, R. Schaffer, S. Siegel, R. Merker, R. Keryell, B. Pottier, D. Chillet, D. Menard, O. Sentieys.
Co-Design of Massively Parallel Embedded Processor Architectures, in: Workshop ReCoSoC 2005, Reconfigurable Communication-Centric SoCs, Montpellier, France, 2005.
[36]
N. Hervé, D. M. et O. Sentieys.
Optimisation de la largeur des opérateurs arithmétiques en synthèse de haut-niveau, in: GRETSI, Louvain, Belgique, November 2005.
[37]
N. Hervé, D. M. et O. Sentieys.
Synthèse d’architecture sur FPGA sous contrainte de précision des calculs, in: RENPAR’16 / CFSE’4 / SympAAA’2005 / Journées Composants, Le Croisic, France, 2005.
[38]
N. Hervé, D. Menard, O. Sentieys.
Data Wordlength Optimization for FPGA Synthesis, in: Proceedings of the IEEE International Workshop on Signal Processing Systems, SIPS'05, Athens, Grece, November 2005.
[39]
N. Hervé, D. Menard, O. Sentieys.
Synthèse d’architecture sur FPGA sous contrainte de précision, in: Majestic 2005, Troisième MAnifestation des JEunes Chercheurs dans les domaines STIC, Rennes, France, 2005.
[40]
V. Ila, R. Garcia, F. Charot.
VLSI Architecture for an Underwater Robot Vision System, in: Proceedings of the OCEANS'05 IEEE International Conference, Brest, France, June 2005.
[41]
L. L'Hours.
Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications, in: Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors, S. Vassiliadis, N. Dimopoulos, S. Rajopadhye (editors), IEEE Computer Society, July 2005, p. 127–133.
[42]
J.-M. Philippe, S. Pillement, O. Sentieys.
A low-power and high-speed quaternary interconnection link using efficient converters, in: ISCAS'05: Proceedings of the International Symposium on Circuits and Systems, IEEE CAS Society, 2005, p. 4689–4692.
[43]
C. Plapous, C. Marro, P. Scalart.
Reliable a posteriori Signal-to-Noise Ration features selection, in: IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, Mohonk Mountain House, New Paltz, New York, 2005.
[44]
C. Plapous, C. Marro, P. Scalart.
Speech enhancement using harmonic regeneration, in: IEEE Int. Conference on Acoustics, Speech, and Signal Processing, ICASSP, Philadelphie, USA, 2005, vol. 5.
[45]
R. Rocher, D. Menard, O. Sentieys, P. Scalart.
Accuracy Evaluation of APA Algorithms, in: IEEE Int. Conference on Acoustics, Speech, and Signal Processing, ICASSP, Philadelphie, USA, 2005, vol. 5, p. 57-60.
[46]
R. Rocher, D. Menard, O. Sentieys, P. Scalart.
Evaluation de la précision des Algorithmes de Projection Affine en Virgule Fixe, in: GRETSI, Louvain, Belgique, 2005.
[47]
T. Saïdi, O. Sentieys, S. Roy.
Prototype MIMO temps réel pour l'UMTS, in: Majestic 2005, Troisième MAnifestation des JEunes Chercheurs dans les domaines STIC, Rennes, France, 2005.
[48]
F. Verdier, J. Prévotet, A. Benkhelifa, D. Chillet, S. Pillement.
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform, in: Workshop ReCoSoC 2005, Reconfigurable Communication-Centric SoCs, Montpellier, France, 2005.
[49]
C. Wolinski, K. Kuchcinski.
A Constraints Programming Approach for Fabric Cell Synthesis, in: Proceedings of the Digital System Design Conference, DSD'05, Porto, Portugal, September 2005.

References in notes

[50]
L. Benini, G. D. Micheli.
Networks on Chips: a New SoC Paradigm, in: IEEE Computer, January 2002, vol. 35, no 1, p. 70–78.
[51]
D. C. Cronquist, P. Franklin, C. Fisher, M. Figueroa, C. Ebeling.
Architecture Design of Reconfigurable Pipelined Datapath, in: Advance Research in VLSI, 1999.
[52]
W. Dally, B. Towles.
Route Packets, Not Wires: on-chip Interconnection Networks, in: Proceedings of the 38th Design Automation Conference, June 2001.
[53]
A. Darte, R. Schreiber, B. R. Rau, F. Vivien.
Constructing and exploiting linear schedules with prescribed parallelism, in: ACM Trans. Des. Autom. Electron. Syst., 2002, vol. 7, no 1, p. 159–172.
[54]
J. da Silva Jr., J. Shamberger, J. Ammer, C. Guo, S. Li, R. Shah, T. Tuan, M. Sheets, J. Rabaey, B. Nikolic, A. Sangiovanni-Vincentelli, P. Wright.
Design Methodology for PicoRadio Networks, in: Design, Automation and Test in Europe Conference, IEEE/ACM, 2001.
[55]
A. DeHon.
Reconfigurable Architecture for General-Purpose Computing, Ph. D. Thesis, MIT, 1996.
[56]
Y. Ephraïm, D. Malah.
Speech Enhancement Using a Minimum Mean-Square Error Short-Time Spectral Amplitude Estimator, in: IEEE Transaction on Acoustic, Speech and Signal Processing, December 1984, vol. ASSP-32, no 6, p. 1109-1121.
[57]
G. Epstein.
Multiple-Valued Logic Design: An introduction, Institute of Physics Publishing, Bristol, 1993.
[58]
A. Goldsmith, S. Wicker.
Design Challenges for Energy-Constrained Ad Hoc Wireless Networks, in: IEEE Wireless Communications, August 2002, vol. 9, no 4, p. 8–27.
[59]
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. R. Taylor.
PipeRench : A Reconfigurable Architecture and Compiler, in: IEEE Computer, April 2000.
[60]
T. Grötker, E. Multhaup, O. Mauss.
Evaluation of HW/SW Tradeoffs Using Behavioral Synthesis, in: ICSPAT'96, Boston, October 1996.
[61]
R. Hartenstein.
A Decade of Reconfigurable Computing : A Visionary retrospective, in: Design Automation and Test in Europe (DATE), 2001.
[62]
J. Hauser, J. Wawrzynek.
GARP : A MIPS processor with a reconfigurable coprocessor, in: IEEE Symposium on FPGAs for Custom Computing Machines, June 1997.
[63]
H. Keding, M. Coors, O. Luthje, H. Meyr.
Fast Bit True Simulation, in: Design Automation Conference 2001 (DAC 2001), Las Vegaus, June 2001.
[64]
K. Keutzer, S. Malik, R. Newton, J. Rabaey, A. Sangiovanni-Vincentelli.
System Level Design : Orthogonalization of Concerns and Platform-based Design, in: IEEE Transactions on Computer-Aided of Circuits and Systems, December 2000, vol. 19, no 12.
[65]
K. Kum, J. Kang, W. Sung.
AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II, September 2000, vol. 47, p. 840-848.
[66]
R. Leupers.
Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997.
[67]
G. Lu, H. Singh, M. Lee, N. Bagherzadeh, F. Kurdahi, E. Filho.
The MorpoSys Parallel Reconfigurable System, in: Euro-Par'99, LNCS 1685, 1999.
[68]
S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr.
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures, in: DAC 1999, June 1999.
[69]
J. Rabaey.
A low-energy heterogeneous reconfigurable DSP IC, in: Design Automation Conference (DAC), June 2000.
[70]
C. Rupp, M. Landguth, T. Graverick, E. Gomersall, H. Holt.
The NAPA Adaptative Processing Architecture, in: IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.
[71]
M. H. S. Hauck, J. Kao.
The Chimera Reconfigurable Functional Unit, in: IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
[72]
A. Sangiovanni-Vincentelli, G. Martin.
Platform-Based Design and Software Design Methodology for Embedded Systems, in: IEEE Design and Test of Computers, November 2001.
[73]
R. Schreiber, S. Aditya, S. Mahle, V. Kathail, B. Rau, D. Cronquist, M. Sivaraman.
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators, Technical report, HP Laboratories Palo Alto, October 2001, no HPL-2001-249.
[74]
M. Srivastava.
Power-aware Communication Systems, in: Power-aware Design Methodologies, M. Pedram, J. Rabaey (editors), Kluwer Academic Publishers, 2002, chap. 11, p. 297–334.
[75]
M. Willems, V. Bursgens, H. Keding, H. Meyr.
System Level Fixed-Point Design Based On An Interpolative Approach, in: Design Automation Conference (DAC-97), 1997.

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