Team R2D2

Overall Objectives
Scientific Foundations
Application Domains
New Results
Contracts and Grants with Industry
Other Grants and Activities
Inria / Raweb 2004
Team: R2D2


Major publications by the team in recent years

F. Charot, G. Le Fol, P. Lemonnier, C. Wagner, C. Bouville, R. Barzic.
Towards Hardware Building Blocks for Software-Only Real Time Video Processing: the MOVIE Approach, in: IEEE Transactions on Circuits and Systems for Video Technology, September 1999, vol. 9, no 6.
R. David, D. Chillet, S. Pillement, O. Sentieys.
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals, in: SOC Design Methodologies, Kluwer Academic Publishers, 2002, p. 51–62.
R. David.
Architecture reconfigurable dynamiquement pour applications mobiles, Thèse de Doctorat, Université de Rennes, July 2003.
F. Dupont de Dinechin.
Systèmes structurés d'équations récurrentes : mise en œuvre dans le langage Alpha et applications, Thèse de doctorat, université de Rennes I, January 1997.
K. Kuchcinski, C. Wolinski.
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, December 2003, vol. 49, no 12-15.
C. Mauras.
Alpha : un langage équationnel pour la conception et la programmation d'architectures parallèles synchrones, Thèse de doctorat, Université de Rennes 1, December 1989.
D. Ménard.
Méthodologie de compilation d'algorithmes de traitement du signal en précision infinie pour les processeurs en virgule fixe, Thèse de doctorat, Université de Rennes 1, December 2002.
V. Messé.
Production de compilateurs flexibles pour la conception de processeurs programmables spécialisés, Thèse de doctorat, Université de Rennes 1, March 1999.
P. Quinton, V. V. Dongen..
The mapping of linear recurrence equations on regular arrays, in: Journal of VLSI Signal Processing, 1989, vol. 1, p. 93-113.
P. Quinton, Y. Robert.
Systolic Algorithms and Architectures, Prentice Hall and Masson, 1989.
S. V. Rajopadhye, S. Purushothaman, R. M. Fujimoto.
On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies, in: Proceedings, Sixth Conference on Foundations of Software Technology and Theoretical Computer Science, New Delhi, India, Springer Verlag, LNCS 241, December 1986, p. 488-503.
C. Wolinski, M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, no 4-6.

Publications of the year

Articles in refereed journals and book chapters

M. Auguin, O. Sentieys.
Conception de systèmes sur puce : nécessité d'approches globales face à la concentration des difficultés, in: Etat des lieux en Architecture, Parallélisme et Système, M. Jemni, D. Trystram (editors), To appear, Hermes, 2004.
R. David, S. Pillement, O. Sentieys.
Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
A.-C. Guillou, P. Quinton, T. Risset.
Hardware Synthesis for Systems of Recurrence Equations with Multidimensional Schedule, in: International Journal on Embedded Systems, To appear, 2004.

Publications in Conferences and Workshops

F. B. Abdallah, S. Pillement, O. Sentieys, A. Bouallegue.
Acceleration of a VLIW Processor With Dynamic Reconfiguration, in: The 16th International Conference on Microelectronics, December 2004.
L. Bélanger, S. Roy, T. Saïdi, O. Sentieys.
Prototyping a MIMO W-CDMA System using a System-Level Approach, in: Proceedings of the International Signal Processing Conference (ISPC) and Global Signal Processing Expo (GSPx), Santa Clara, USA, September 2004.
J. Cambonie, S. Guérin, R. Keryell, L. Lagadec, B. Pottier, O. Sentieys, B. Weber, S. Yazdani.
Compiler and System Techniques for SoC Distributed Reconfigurable Accelerators, in: Proceedings of the Fourth International Workshop on Systems, Architectures, MOdeling, and Simulation SAMOS IV, Samos, Greece, July 2004.
F. Charot, L. L'Hours.
Rôle des langages de description d'architectures dans le processus de conception de SoC, in: Proceedings of the first congress on <<Signaux, Circuits et Systèmes>>, Monastir, Tunisia, March 2004.
F. Charot, M. Nyamsi, P. Quinton, C. Wagner.
Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform, in: Proceedings of the Fourth International Workshop on Systems, Architectures, MOdeling, and Simulation SAMOS IV, Samos, Greece, July 2004.
F. Charot, M. Nyamsi, P. Quinton, C. Wagner.
Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations, in: Proceedings of the 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP'04), Galveston, Texas, US, September 2004.
M. Gokhale, C. Ahrens, J. Frigo, C. Wolinski.
Communications Scheduling for Concurrent Processes on Reconfigurable Computers, in: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), Napa Valley, California, US, April 2004.
V. Ila, R. Garcia, F. Charot, J. Batlle.
FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot, in: Proceedings of the International Conference on Field Programmable Logic and its Applications (FPL'04), Antwerp, Belgium, September 2004.
V. Ila, R. Garcia, F. Charot.
Proposal of a Parallel Architecture for a Motion Detection Algorithm, in: Proceedings of the 17th International Conference on Pattern Recognition (ICPR'04), Cambridge, UK, August 2004.
D. Menard, R. Rocher, P. Scalart, O. Sentieys.
SQNR Determination in Non-Linear and Non-Recursive Fixed-Point Systems, in: XII European Signal Processing Conference (EUSIPCO 2004), Vienna, Austria, September 2004, p. 1349-1352.
D. Menard, O. Sentieys.
DSP Code Generation with Optimized Data-Word Length Selection , in: 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES'04), Amsterdam, Netherlands, September 2004.
C. Plapous, C. Marro, L. Mauuary, P. Scalart.
A Two-Step Noise Reduction Technique , in: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP'04), Montreal, Canada, May 2004.
R. Rocher, D. Menard, P. Scalart, O. Sentieys.
Accuracy Evaluation of Fixed-Point LMS Algorithm, in: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP'04), Montreal, Canada, May 2004, p. 237-240.
N. Ventroux, S. Chevobbe, F. Blanc, T. Collette.
An Auto-adaptative Reconfigurable Architecture for the Control, in: Proceedings of the 9th Asia-Pacific Computer Systems Architecture Conference (ACSAC'04), Beijing, China, September 2004.
C. Wolinski, K. Kuchcinski, M. Gokhale.
A Constraints Programming Approach to Communication Scheduling on SoPC Architectures, in: Proceedings of the Euromicro Symposium on Digital System Design, Rennes, France, September 2004.
C. Wolinski, K. Kuchcinski, M. Gokhale.
A Constraints Programming Approach to Communication Scheduling, in: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'04), Monterey, California, US, February 2004.

References in notes

L. Benini, G. D. Micheli.
Networks on Chips: a New SoC Paradigm, in: IEEE Computer, January 2002, vol. 35, no 1, p. 70–78.
D. C. Cronquist, P. Franklin, C. Fisher, M. Figueroa, C. Ebeling.
Architecture Design of Reconfigurable Pipelined Datapath, in: Advance Research in VLSI, 1999.
W. Dally, B. Towles.
Route Packets, Not Wires: on-chip Interconnection Networks, in: Proceedings of the 38th Design Automation Conference, June 2001.
J. da Silva Jr., J. Shamberger, J. Ammer, C. Guo, S. Li, R. Shah, T. Tuan, M. Sheets, J. Rabaey, B. Nikolic, A. Sangiovanni-Vincentelli, P. Wright.
Design Methodology for PicoRadio Networks, in: Design, Automation and Test in Europe Conference, IEEE/ACM, 2001.
A. DeHon.
Reconfigurable Architecture for General-Purpose Computing, Ph. D. Thesis, MIT, 1996.
G. Epstein.
Multiple-Valued Logic Design: An introduction, Institute of Physics Publishing, Bristol, 1993.
A. Goldsmith, S. Wicker.
Design Challenges for Energy-Constrained Ad Hoc Wireless Networks, in: IEEE Wireless Communications, August 2002, vol. 9, no 4, p. 8–27.
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. R. Taylor.
PipeRench : A Reconfigurable Architecture and Compiler, in: IEEE Computer, April 2000.
T. Grötker, E. Multhaup, O. Mauss.
Evaluation of HW/SW Tradeoffs Using Behavioral Synthesis, in: ICSPAT'96, Boston, October 1996.
R. Hartenstein.
A Decade of Reconfigurable Computing : A Visionary retrospective, in: Design Automation and Test in Europe (DATE), 2001.
S. Hauck, T.W Fry, M.M. Hosler, J. Kao.
The Chimera Reconfigurable Functional Unit, in: IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
J. Hauser, J. Wawrzynek.
GARP : A MIPS processor with a reconfigurable coprocessor, in: IEEE Symposium on FPGAs for Custom Computing Machines, June 1997.
H. Keding, M. Coors, O. Luthje, H. Meyr.
Fast Bit True Simulation, in: Design Automation Conference 2001 (DAC 2001), Las Vegaus, June 2001.
K. Keutzer, S. Malik, R. Newton, J. Rabaey, A. Sangiovanni-Vincentelli.
System Level Design : Orthogonalization of Concerns and Platform-based Design, in: IEEE Transactions on Computer-Aided of Circuits and Systems, December 2000, vol. 19, no 12.
K. Kum, J. Kang, W. Sung.
AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II, September 2000, vol. 47, p. 840-848.
R. Leupers.
Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997.
G. Lu, H. Singh, M. Lee, N. Bagherzadeh, F. Kurdahi, E. Filho.
The MorpoSys Parallel Reconfigurable System, in: Euro-Par'99, LNCS 1685, 1999.
S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr.
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures, in: DAC 1999, June 1999.
J. Rabaey.
A low-energy heterogeneous reconfigurable DSP IC, in: Design Automation Conference (DAC), June 2000.
C. Rupp, M. Landguth, T. Graverick, E. Gomersall, H. Holt.
The NAPA Adaptative Processing Architecture, in: IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.
A. Sangiovanni-Vincentelli, G. Martin.
Platform-Based Design and Software Design Methodology for Embedded Systems, in: IEEE Design and Test of Computers, November 2001.
R. Schreiber, S. Aditya, S. Mahle, V. Kathail, B. Rau, D. Cronquist, M. Sivaraman.
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators, Technical report, HP Laboratories Palo Alto, October 2001, no HPL-2001-249.
M. Srivastava.
Power-aware Communication Systems, in: Power-aware Design Methodologies, M. Pedram, J. Rabaey (editors), Kluwer Academic Publishers, 2002, chap. 11, p. 297–334.
M. Willems, V. Bursgens, H. Keding, H. Meyr.
System Level Fixed-Point Design Based On An Interpolative Approach, in: Design Automation Conference (DAC-97), 1997.