Team R2D2

Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Other Grants and Activities
Dissemination
Bibliography
Inria / Raweb 2003
Team: R2D2

Bibliography

Major publications by the team in recent years

[1]
F. Charot , G. Le Fol, P. Lemonnier, C. Wagner , C. Bouville, R. Barzic.
Towards Hardware Building Blocks for Software-Only Real Time Video Processing: the MOVIE Approach, in: IEEE Transactions on Circuits and Systems for Video Technology, September 1999, vol. 9, no 6.
[2]
R. David , D. Chillet , S. Pillement , O. Sentieys .
SOC Design Methodologies, Kluwer Academic Publishers, 2002, chap. A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals, p. 51–62.
[3]
J. Diguet, D. Chillet , O. Sentieys .
A Framework for High Level Estimations of Signal Processing Implementations, in: Journal of VLSI System for Signal, Image and Video Technology, July 2000, vol. 25, no 3.
[4]
F. Dupont de Dinechin.
Systèmes structurés d'équations récurrentes : mise en œuvre dans le langage Alpha et applications, Thèse de doctorat, université de Rennes I, January 1997.
[5]
C. Mauras.
Alpha : un langage équationnel pour la conception et la programmation d'architectures parallèles synchrones, Thèse de doctorat, Université de Rennes 1, December 1989.
[6]
D. Menard , O. Sentieys .
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
[7]
D. Ménard.
Méthodologie de compilation d'algorithmes de traitement du signal en précision infinie pour les processeurs en virgule fixe, Thèse de doctorat, Université de Rennes 1, December 2002.
[8]
V. Messé.
Production de compilateurs flexibles pour la conception de processeurs programmables spécialisés, Thèse de doctorat, Université de Rennes 1, March 1999.
[9]
P. Quinton , V. V. Dongen..
The mapping of linear recurrence equations on regular arrays, in: Journal of VLSI Signal Processing, 1989, vol. 1, p. 93-113.
[10]
P. Quinton , Y. Robert.
Systolic Algorithms and Architectures, Prentice Hall and Masson, 1989.
[11]
S. V. Rajopadhye, S. Purushothaman, R. M. Fujimoto.
On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies, in: Proceedings, Sixth Conference on Foundations of Software Technology and Theoretical Computer Science, New Delhi, India, Springer Verlag, LNCS 241, December 1986, p. 488-503.

Year Publications

Doctoral dissertations and Habilitation theses

[12]
R. David .
Architecture reconfigurable dynamiquement pour applications mobiles, Thèse de Doctorat, Université de Rennes, July 2003.
[13]
A.-C. Guillou .
Synthèse architecturale basée sur le modèle polyédrique : validation et extensions de la méthodologie MMAlpha, Thèse de Doctorat, Université de Rennes, December 2003.

Articles in refereed journals and book chapters

[14]
R. David , D. Lavenier, S. Pillement .
Du microprocesseur au circuit FPGA : une analyse sous l'angle de la reconfiguration, in: Technique et Science Informatiques, to appear, 2003.
[15]
R. David , S. Pillement , O. Sentieys .
Low Power Electronics Design, To appear, CRC Press, 2003, chap. Energy-Efficient Reconfigurable Processsors.
[16]
S. Derrien , A.-C. Guillou , P. Quinton , T. Risset , C. Wagner .
Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures, in: Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, S. Bhattacharyya, E. Deprettere, J. Teich (editors), To appear, Marcel Dekker, 2003, chap. 10.
[17]
M. Gokhale, J. Frigo, K. McCabe, J. Theiler, C. Wolinski , D. Lavenier.
Experience with a Hybrid Processor: K-Means Clustering, in: Special Issues of the Journal of Supercomputing, 2003, vol. 24, no 4.
[18]
K. Kuchcinski, C. Wolinski .
Global Approach to Scheduling Complex Behaviors based on Hierarchical Conditional Dependency Graphs and Constraint Programming, in: Journal of Systems Architecture, to appear, 2003.
[19]
D. Menard , T. Saïdi , D. Chillet , O. Sentieys .
Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe, in: Technique et Science Informatiques, 2003, vol. 22, no 2, p. 783-809.
[20]
C. Wolinski , M. Gokhale, K. McCabe.
Polymorphous fabric-based systems: Model, tools, applications, in: Journal of Systems Architecture, September 2003, vol. 49, no 4-6.

Publications in Conferences and Workshops

[21]
I. Benkermi , S. Pillement , O. Sentieys .
Application des réseaux de neurones à l'ordonnancement de tâches temps réel sur une architecture multiprocesseurs hétérogènes, in: SYMPposium en Architectures nouvelles de machines, SympA'2003, La Colle sur Loup, France, October 2003, p. 372–379.
[22]
F. Bouteille, P. Scalart , B. Kovesi.
Packet loss concealment using audio morphing, in: Speech processing, Transmission and Quality aspects (STQ) Workshop Compensating for Packet Loss in Real-Time Applications, February 2003.
[23]
S. Bruno, P. Scalart .
Application des techniques de démodulation AM/FM à l'estimation du pouls et de la respiration à partir de signaux biomédicaux, in: Colloque GRETSI sur le traitement du signal et des images 2003, Paris, France, September 2003.
[24]
S. Bruno, P. Scalart .
Smart Multisensor Kernel, in: Smart Objects Conference SOC'2003, May 2003.
[25]
F. Charot , E. yahya.
Fully-Modular Partially-Pipelined AES Implementation in Counter Mode using ALTERA FPGA, in: Proceedings of 2003 International Conference on Electronic Sciences, Information Technology and Telecommunication, Susa, Tunisia, March 2003.
[26]
F. Charot , E. yahya, C. Wagner .
Efficient Modular-Pipelined AES Implementation in Counter Mode on ALTERA FPGA, in: Proceedings of FPL 03, Lisbon, Portugal, LNCS 2778, September 2003, p. 282–291.
[27]
S. Chevobbe , N. Ventroux, F. Blanc, T. Collette.
RAMPASS: Reconfigurable And Advanced Multi-Processing Architecture for future Silicon System, in: Proceedings of Samos III Workshop, July 2003.
[28]
H. Gnaba, M. Jaidane-Saidane, P. Scalart .
Introduction of the CELP structure of the GSM coder in the acoustic echo canceller for the GSM network, in: 8th European Conference on Speech Communication and Technology, September 2003.
[29]
A.-C. Guillou , P. Quinton , T. Risset .
Hardware Synthesis for Multi-Dimensional Time, in: Proceedings of ASAP 03, The Hague, The Netherlands, IEEE Press, June 2003, p. 40–51no.
[30]
E. Kinvi-Boh , M. Aline , O. Sentieys .
Conception d'un processeur ternaire à faible énergie, in: Colloque Faible Tension Faible Consommation (FTFC'03), May 2003.
[31]
E. Kinvi-Boh , M. Aline , O. Sentieys , E. Olson.
Design and Characterization of a Low-Power Ternary DSP, in: International Signal Processing Conference (ISPC'03), Dallas, US, April 2003.
[32]
E. Kinvi-Boh , M. Aline , O. Sentieys , E. Olson.
MVL Circuit Design and Characterization using SUS-LOC structure, in: IEEE International Symposium on Multiple-Valued Logic (ISMVL'03), Tokyo, Japan, May 2003.
[33]
D. Lavenier, S. Guyétant, S. Derrien , S. Rubini.
A reconfigurable parallel disk system for filtering genomic banks, in: Engineering of Reconfigurable Systems and Algorithms, 2003no.
[34]
D. Massicotte, P. Quinton , A. O. Dahmane, T. Risset .
Fast Exploration of Parallel Architectures for Multi-User Detection Algorithms: A Case Study, in: Proceedings of Samos III Workshop, July 2003.
[35]
D. Menard , M. Guitton , R. David , S. Pillement , O. Sentieys .
Évaluation comparative de plates-formes reconfigurables et programmables pour les télécommunications de 3ème génération, in: Colloque GRETSI sur le traitement du signal et des images 2003, Paris, France, September 2003.
[36]
D. Menard , M. Guitton , S. Pillement , O. Sentieys .
Design and Implementation of WCDMA Platforms: Challenges and Trade-offs, in: International Signal Processing Conference (ISPC'03), Dallas, US, April 2003.
[37]
D. Menard , M. Guitton , P. Quemerais, O. Sentieys .
Efficient Implementation of a WCMA Rake Receiver on the TMS320C64x, in: 37th Asilomar Conference on Signals, Systems and Computers, Monterey, US, November 2003.
[38]
S. Pillement , R. David , O. Sentieys .
Architectures reconfigurables : opportunités pour la faible consommation, in: Colloque Faible Tension Faible Consommation (FTFC'03), May 2003.
[39]
C. Wolinski , M. Gokhale, K. McCabe.
Fabric-Based Systems: Model, Tools, Applications, in: IEEE Symposium on Field-Programmable Custom Computing Machines, April 2003.
[40]
C. Wolinski , M. Gokhale, K. McCabe.
Rapid Construction of Reconfigurable Computing Fabrics for Systems on a Programmable Chip, in: IEEE HPCA/SSRS '03, February 2003.
[41]
C. Wolinski , F. Trouw, M. Gokhale.
A Preliminary Study of Molecular Dynamics on Reconfigurable Computers, in: ERSA'03, February 2003.

References in notes

[42]
D. C. Cronquist, P. Franklin, C. Fisher, M. Figueroa, C. Ebeling.
Architecture Design of Reconfigurable Pipelined Datapath, in: Advance Research in VLSI, 1999.
[43]
A. DeHon.
Reconfigurable Architecture for General-Purpose Computing, Ph. D. Thesis, MIT, 1996.
[44]
G. Epstein.
Multiple-Valued Logic Design: An introduction, Institute of Physics Publishing, Bristol, 1993.
[45]
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. R. Taylor.
PipeRench : A Reconfigurable Architecture and Compiler, in: IEEE Computer, April 2000.
[46]
T. Grötker, E. Multhaup, O. Mauss.
Evaluation of HW/SW Tradeoffs Using Behavioral Synthesis, in: ICSPAT'96, Boston, October 1996.
[47]
R. Hartenstein.
A Decade of Reconfigurable Computing : A Visionary retrospective, in: Design Automation and Test in Europe (DATE), 2001.
[48]
S. Hauck, J. Kao.
The Chimera Reconfigurable Functional Unit, in: IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
[49]
J. Hauser, J. Wawrzynek.
GARP : A MIPS processor with a reconfigurable coprocessor, in: IEEE Symposium on FPGAs for Custom Computing Machines, June 1997.
[50]
H. Keding, M. Coors, O. Luthje, H. Meyr.
Fast Bit True Simulation, in: Design Automation Conference 2001 (DAC 2001), Las Vegaus, June 2001.
[51]
K. Keutzer, S. Malik, R. Newton, J. Rabaey, A. Sangiovanni-Vincentelli.
System Level Design : Orthogonalization of Concerns and Platform-based Design, in: IEEE Transactions on Computer-Aided of Circuits and Systems, December 2000, vol. 19, no 12.
[52]
K. Kum, J. Kang, W. Sung.
AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II, September 2000, vol. 47, p. 840-848.
[53]
R. Leupers.
Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997.
[54]
G. Lu, H. Singh, M. Lee, N. Bagherzadeh, F. Kurdahi, E. Filho.
The MorpoSys Parallel Reconfigurable System, in: Euro-Par'99, LNCS 1685, 1999.
[55]
C. Mauras.
Alpha : un langage équationnel pour la conception et la programmation d'architectures parallèles synchrones, Ph. D. Thesis, Université de Rennes 1, December 1989.
[56]
J. Nechvatal, E. Barker, L. Bassham, W. Burr, M. Dworkin, J. Foti, E. Roback.
Report on the developement of the Advanced Encryption Standard (AES), Technical report, National Institute of Standard and Technology, October 2000.
[57]
S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr.
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures, in: DAC 1999, June 1999.
[58]
J. Rabaey.
A low-energy heterogeneous reconfigurable DSP IC, in: Design Automation Conference (DAC), June 2000.
[59]
C. Rupp, M. Landguth, T. Graverick, E. Gomersall, H. Holt.
The NAPA Adaptative Processing Architecture, in: IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.
[60]
A. Sangiovanni-Vincentelli, G. Martin.
Platform-Based Design and Software Design Methodology for Embedded Systems, in: IEEE Design and Test of Computers, November 2001.
[61]
R. Schreiber, S. Aditya, S. Mahle, V. Kathail, B. Rau, D. Cronquist, M. Sivaraman.
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators, Technical report, HP Laboratories Palo Alto, October 2001, no HPL-2001-249.
[62]
M. Willems, V. Bursgens, H. Keding, H. Meyr.
System Level Fixed-Point Design Based On An Interpolative Approach, in: Design Automation Conference (DAC-97), 1997.

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