Team R2D2

Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Other Grants and Activities
Dissemination
Bibliography
Inria / Raweb 2002
Project: R2D2

Bibliography

Major publications by the team in recent years

[1]
F. Charot , G. Le Fol, P. Lemonnier, C. Wagner , C. Bouville, R. Barzic.
Towards Hardware Building Blocks for Software-Only Real Time Video Processing : the MOVIE Approach, in: IEEE Transactions on Circuits and Systems for Video Technology, September 1999, vol. 9, no 6.
[2]
F. Dupont de Dinechin.
Systèmes structurés d'équations récurrentes : mise en œuvre dans le langage Alpha et applications, Thèse de doctorat, université de Rennes I, janvier 1997.
[3]
C. Mauras.
Alpha : un langage équationnel pour la conception et la programmation d'architectures parallèles synchrones, Thèse, Université de Rennes 1, décembre 1989.
[4]
V. Messé.
Production de compilateurs flexibles pour la conception de processeurs programmables spécialisés, thèse, Université de Rennes 1, mars 1999.
[5]
P. Quinton , V. V. Dongen..
The mapping of linear recurrence equations on regular arrays, in: Journal of VLSI Signal Processing, 1989, vol. 1, p. 93-113.
[6]
P. Quinton , Y. Robert.
Systolic Algorithms and Architectures, Prentice Hall and Masson, 1989.
[7]
S. V. Rajopadhye , S. Purushothaman, R. M. Fujimoto.
On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies, in: Proceedings, Sixth Conference on Foundations of Software Technology and Theoretical Computer Science, New Delhi, India, Springer Verlag, LNCS 241, décembre 1986, p. 488-503.

Year Publications

Doctoral dissertations and Habilitation theses

[8]
A. Buisson .
Implémentation efficace d'un codeur vidéo hiérarchique granulaire sur une architecture à processeurs multimédia, thèse, Université de Rennes 1, octobre 2002.
[9]
M. Denoual.
Estimation de haut niveau de la consommation de systèmes sur silicium, thèse, Université de Rennes 1, octobre 2001.
[10]
S. Derrien .
Techniques de partitionnement pour l'implantation de réseaux de processeurs sur FPGA, thèse, Université de Rennes 1, décembre 2002.
[11]
F. Djieya.
Contributions à la conception de systèmes de contrôle de trafic et de gestion de ressources en ATM, thèse, Université de Rennes 1, décembre 2002.
[12]
D. Ménard.
Méthodologie de compilation d'algorithmes de traitement du signal en précision infinie pour les processeurs en virgule fixe, thèse, Université de Rennes 1, décembre 2002.
[13]
R. Yu.
Estimation de haut niveau du placement et des interconnexions dans les circuits VLSI submicroniques, thèse, Université de Rennes 1, mai 2002.

Articles in refereed journals and book chapters

[14]
R. David , D. Chillet , S. Pillement , O. Sentieys .
SOC Design Methodologies, Kluwer Academic Publishers, 2002, chap. A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals, p. 51-62.
[15]
P. Quinton , T. Risset .
Structured Scheduling of Recurrence Equations : Theory and Practice, in: Lecture Notes in Computer Science, 2002, vol. 2268no.

Publications in Conferences and Workshops

[16]
D. Cachera , T. Risset .
Advances in Bit Width Selection Methodology, in: Proc. Application-Specific Systems, Architectures and Processors, San Jose, CA, IEEE, juillet 2002, p. 381-390.
[17]
R. David , D. Chillet , S. Pillement , O. Sentieys .
Mapping Future Generation Mobile Telecommunication Applications on a Dynamically Reconfigurable Architecture, in: IEEE International Conference on Acoustic Speech, and Signal Processing ICASSP 2002, mai 2002.
[18]
R. David , D. Chillet , S. Pillement , O. Sentieys .
A Compilation Framework for a Dynamically Reconfigurable Architecture, in: 12th IEEE International Conference on Field Programmable Logic and Applications, FPL 2002, Lecture Notes in Computer Science, Springer CS Press, septembre 2002, vol. 2438.
[19]
R. David , D. Chillet , S. Pillement , O. Sentieys .
A High-Performance dynamically reconfigurable embedded architecture, in: Sophia Antipolis Conference on Microelectronics SAME'2002, 2002.
[20]
R. David , D. Chillet , S. Pillement , O. Sentieys .
DART : A Dynamically Reconfigurable Architecture dealing with Next Generation Telecommunications Constraints, in: 9th IEEE Reconfigurable Architecture Workshop RAW, IEEE CS Press, avril 2002.
[21]
S. Derrien , A. Guillou , P. Quinton , T. Risset , C. Wagner .
Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures, in: Proc. of the System Architecture Modeling and Simulation Workshop, Samos, Greece, Lecture Notes in Computer Science, Springer Verlag, 2002.
[22]
S. Derrien , S. Rajopadhye .
Energy/power estimation of regular processor arrays, in: Proceedings of the 15th international symposium on System Synthesis, ACM Press, 2002, p. 50-55.
[23]
G. Gupta , S. Rajopadhye , P. Quinton .
Scheduling Reductions on Realistic Machines, in: Proceedings of the fourteenth annual ACM Symposium on Parallel Algorithms and Architectures, ACM Press, 2002, p. 117-126.
[24]
D. Menard , D. Chillet , F. Charot , O. Sentieys .
Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: International Conference on Compilers, Architectures and Synthesis for Embedded Systems 2002 (CASES 2002), Grenoble, octobre 2002.
[25]
D. Menard , P. Quemerais, O. Sentieys .
Influence of fixed-point DSP architecture on computation accuracy, in: XI European Signal Processing Conference (EUSIPCO 2002) , Toulouse, septembre 2002.
[26]
D. Menard , O. Sentieys .
Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe, in: Symposium en Architectures Nouvelles de Machines SYMPA'8, Avril 2002.
[27]
D. Menard , O. Sentieys .
A methodology for evaluating the precision of fixed-point systems, in: IEEE International Conference on Acoustic Speech, and Signal Processing ICASSP 2002, Orlando, mai 2002.
[28]
D. Menard , O. Sentieys .
Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, mars 2002.
[29]
S. Pillement , D. Chillet , O. Sentieys .
A Virtual Component for Motion Estimation Algorithm, in: ERSA'02 : 2002 International Conference on Engineering of Reconfigurable Systems and Algorithms, juin 2002.
[30]
P. Quinton .
Compiling Algorithms to High-Performance Hardware : A Step towards SoC Design, Annual Conference of the Advances School for Computing and Imaging, ASCII 2002, Lochem, The Netherlands, juin 2002.
[31]
O. Sentieys , S. Pillement , D. Chillet .
Behavioral IP Specification and Integration Framework for High-Level Design Reuse, in: ISQED 2002, IEEE International Symposium on Quality Electronic Design, mars 2002.

Internal Reports

[32]
D. Cachera , T. Risset .
Advances in Bit Width Selection Methodology, rapport technique, Irisa, Campus de Beaulieu, Rennes, avril 2002, no 1458.

References in notes

[33]
D. C. Cronquist, P. Franklin, C. Fisher, M. Figueroa, C. Ebeling.
Architecture Design of Reconfigurable Pipelined Datapath, in: Advance Research in VLSI, 1999.
[34]
A. DeHon.
Reconfigurable Architecture for General-Purpose Computing, thèse de doctorat, MIT, 1996.
[35]
G. Epstein.
Multiple-Valued Logic Design : An introduction, Institute of Physics Publishing, Bristol, 1993.
[36]
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. R. Taylor.
PipeRench : A Reconfigurable Architecture and Compiler, in: IEEE Computer, avril 2000.
[37]
T. Grötker, E. Multhaup, O. Mauss.
Evaluation of HW/SW Tradeoffs Using Behavioral Synthesis, in: ICSPAT'96, Boston, octobre 1996.
[38]
R. Hartenstein.
A Decade of Reconfigurable Computing : A Visionary retrospective, in: Design Automation and Test in Europe (DATE), 2001.
[39]
S. Hauck, J. Kao.
The Chimera Reconfigurable Functional Unit, in: IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
[40]
J. Hauser, J. Wawrzynek.
GARP : A MIPS processor with a reconfigurable coprocessor, in: IEEE Symposium on FPGAs for Custom Computing Machines, juin 1997.
[41]
H. Keding, M. Coors, O. Luthje, H. Meyr.
Fast Bit True Simulation, in: Design Automation Conference 2001 (DAC 2001), Las Vegaus, juin 2001.
[42]
K. Keutzer, S. Malik, R. Newton, J. Rabaey, A. Sangiovanni-Vincentelli.
System Level Design : Orthogonalization of Concerns and Platform-based Design, in: IEEE Transactions on Computer-Aided of Circuits and Systems, décembre 2000, vol. 19, no 12.
[43]
K. Kum, J. Kang, W. Sung.
AUTOSCALER for C : An optimizing floating-point to integer C program converter for fixed-point digital signal processors, in: IEEE Transactions on Circuits and Systems II, septembre 2000, vol. 47, p. 840-848.
[44]
R. Leupers.
Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997.
[45]
G. Lu, H. Singh, M. Lee, N. Bagherzadeh, F. Kurdahi, E. Filho.
The MorpoSys Parallel Reconfigurable System, in: Euro-Par'99, LNCS 1685, 1999.
[46]
J. Nechvatal, E. Barker, L. Bassham, W. Burr, M. Dworkin, J. Foti, E. Roback.
Report on the developement of the Advanced Encryption Standard (AES), rapport technique, National Institute of Standard and Technology, octobre 2000.
[47]
E. Olson.
Supplementary Symmetrical Logic Circuit Structure, in: IEEE International Symposium on Multiple-Valued Logic, 1999.
[48]
S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr.
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures, in: DAC 1999, juin 1999.
[49]
J. Rabaey.
A low-energy heterogeneous reconfigurable DSP IC, in: Design Automation Conference (DAC), juin 2000.
[50]
C. Rupp, M. Landguth, T. Graverick, E. Gomersall, H. Holt.
The NAPA Adaptative Processing Architecture, in: IEEE Symposium on FPGAs for Custom Computing Machines, avril 1998.
[51]
A. Sangiovanni-Vincentelli, G. Martin.
Platform-Based Design and Software Design Methodology for Embedded Systems, in: IEEE Design and Test of Computers, novembre 2001.
[52]
R. Schreiber, S. Aditya, S. Mahle, V. Kathail, B. Rau, D. Cronquist, M. Sivaraman.
PICO-NPA : High-Level Synthesis of Nonprogrammable Hardware Accelerators, rapport technique, HP Laboratories Palo Alto, octobre 2001, no HPL-2001-249.
[53]
M. Willems, V. Bursgens, H. Keding, H. Meyr.
System Level Fixed-Point Design Based On An Interpolative Approach, in: Design Automation Conference (DAC-97), 1997.

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